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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">SDCR, Secure Debug Control Register</h1><p>The SDCR characteristics are:</p><h2>Purpose</h2>
        <p>Provides EL3 configuration options for self-hosted debug, trace, and the Performance Monitors Extension.</p>
      <h2>Configuration</h2><p>This register is present only when EL3 is capable of using AArch32. Otherwise, direct accesses to SDCR are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>SDCR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="3"><a href="#fieldset_0-31_29">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-28_28-1">MTPME</a></td><td class="lr" colspan="1"><a href="#fieldset_0-27_27-1">TDCC</a></td><td class="lr" colspan="3"><a href="#fieldset_0-26_24">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-23_23-1">SCCD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-22_22">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-21_21-1">EPMAD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20-1">EDAD</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19-1">TTRF</a></td><td class="lr" colspan="1"><a href="#fieldset_0-18_18-1">STE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-17_17-1">SPME</a></td><td class="lr" colspan="1"><a href="#fieldset_0-16_16">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_14">SPD</a></td><td class="lr" colspan="14"><a href="#fieldset_0-13_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-31_29">Bits [31:29]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-28_28-1">MTPME, bit [28]<span class="condition"><br/>When FEAT_MTPMU is implemented:
                        </span></h4><div class="field">
      <p>Multi-threaded PMU Enable. Enables use of the <a href="AArch32-pmevtypern.html">PMEVTYPER&lt;n&gt;</a>.MT bits.</p>
    <table class="valuetable"><tr><th>MTPME</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><span class="xref">FEAT_MTPMU</span> is disabled. The Effective value of <a href="AArch32-pmevtypern.html">PMEVTYPER&lt;n&gt;</a>.MT is 0.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="AArch32-pmevtypern.html">PMEVTYPER&lt;n&gt;</a>.MT bits not affected by this bit.</p>
        </td></tr></table>
      <p>If <span class="xref">FEAT_MTPMU</span> is disabled for any other PE in the system that has the same level 1 Affinity as the PE, it is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether the PE behaves as if this bit is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Cold reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">1</span>.
</li></ul></div><h4 id="fieldset_0-28_28-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-27_27-1">TDCC, bit [27]<span class="condition"><br/>When FEAT_FGT is implemented:
                        </span></h4><div class="field">
      <p>Trap DCC. Traps use of the Debug Comms Channel in modes other than Monitor mode to Monitor mode.</p>
    <table class="valuetable"><tr><th>TDCC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This control does not cause any register accesses to be trapped.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Accesses to the DCC registers in modes other than Monitor mode generate a Monitor Trap exception, unless the access also generates a higher priority exception.</p>
<p>Traps on the DCC data transfer registers are ignored when the PE is in Debug state.</p></td></tr></table><p>The DCC registers trapped by this control are:</p>
<ul>
<li><a href="AArch32-dbgdtrrxext.html">DBGDTRRXext</a>, <a href="AArch32-dbgdtrtxext.html">DBGDTRTXext</a>, <a href="AArch32-dbgdscrint.html">DBGDSCRint</a>, <a href="AArch32-dbgdccint.html">DBGDCCINT</a>, and, when the PE is in Non-debug state, <a href="AArch32-dbgdtrrxint.html">DBGDTRRXint</a> and <a href="AArch32-dbgdtrtxint.html">DBGDTRTXint</a>.
</li></ul>
<p>When the PE is in Debug state, SDCR.TDCC does not trap any accesses to:</p>
<ul>
<li><a href="AArch32-dbgdtrrxint.html">DBGDTRRXint</a> and <a href="AArch32-dbgdtrtxint.html">DBGDTRTXint</a>.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-27_27-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-26_24">Bits [26:24]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-23_23-1">SCCD, bit [23]<span class="condition"><br/>When FEAT_PMUv3p5 is implemented:
                        </span></h4><div class="field">
      <p>Secure Cycle Counter Disable. Prohibits <a href="AArch32-pmccntr.html">PMCCNTR</a> from counting in Secure state.</p>
    <table class="valuetable"><tr><th>SCCD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Cycle counting by <a href="AArch32-pmccntr.html">PMCCNTR</a> is not affected by this mechanism.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Cycle counting by <a href="AArch32-pmccntr.html">PMCCNTR</a> is prohibited in Secure state.</p>
        </td></tr></table>
      <p>This field does not affect the CPU_CYCLES event or any other event that counts cycles.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-23_23-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-22_22">Bit [22]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-21_21-1">EPMAD, bit [21]<span class="condition"><br/>When FEAT_Debugv8p4 is implemented and FEAT_PMUv3 is implemented:
                        </span></h4><div class="field">
      <p>External Performance Monitors Non-secure access disable. Controls Non-secure access to Performance Monitors registers by an external debugger.</p>
    <table class="valuetable"><tr><th>EPMAD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Non-secure access to the Performance Monitors registers from an external debugger is permitted.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Non-secure access to the Performance Monitors registers from an external debugger is not permitted.</p>
        </td></tr></table><p>If the Performance Monitors Extension does not support external debug interface accesses, this bit is <span class="arm-defined-word">RES0</span>.</p>
<p>Otherwise, if EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, then the Effective value of this field is 1.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-21_21-2"><span class="condition"><br/>When FEAT_PMUv3 is implemented:
                        </span></h4><div class="field">
      <p>External Performance Monitors access disable. Controls access to Performance Monitors registers by an external debugger.</p>
    <table class="valuetable"><tr><th>EPMAD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Access to Performance Monitors registers from an external debugger is permitted.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Access to Performance Monitors registers from an external debugger is not permitted, unless overridden by the <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> authentication interface.</p>
        </td></tr></table><p>If the Performance Monitors Extension does not support external debug interface accesses, this bit is <span class="arm-defined-word">RES0</span>.</p>
<p>Otherwise, if EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, then the Effective value of this field is 1.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-21_21-3"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-20_20-1">EDAD, bit [20]<span class="condition"><br/>When FEAT_Debugv8p4 is implemented:
                        </span></h4><div class="field">
      <p>External debug Non-secure access disable. Controls Non-secure access to breakpoint, watchpoint, and <a href="ext-oslar_el1.html">OSLAR_EL1</a> registers by an external debugger.</p>
    <table class="valuetable"><tr><th>EDAD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Non-secure access to debug registers from an external debugger is permitted.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Non-secure access to breakpoint registers, watchpoint registers, and <a href="ext-oslar_el1.html">OSLAR_EL1</a> from an external debugger is not permitted.</p>
        </td></tr></table>
      <p>If EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, then the Effective value of this field is 1.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-20_20-2"><span class="condition"><br/>When FEAT_Debugv8p2 is implemented:
                        </span></h4><div class="field">
      <p>External debug access disable. Controls access to breakpoint, watchpoint, and <a href="ext-oslar_el1.html">OSLAR_EL1</a> registers by an external debugger.</p>
    <table class="valuetable"><tr><th>EDAD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Access to debug registers from an external debugger is permitted.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Access to breakpoint registers, watchpoint registers, and <a href="ext-oslar_el1.html">OSLAR_EL1</a> from an external debugger is not permitted, unless overridden by the <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> authentication interface.</p>
        </td></tr></table>
      <p>If EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, then the Effective value of this field is 1.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-20_20-3"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>External debug access disable. Controls access to breakpoint, watchpoint, and optionally <a href="ext-oslar_el1.html">OSLAR_EL1</a> registers by an external debugger.</p>
    <table class="valuetable"><tr><th>EDAD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Access to debug registers from an external debugger is permitted.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td><p>Access to breakpoint registers and watchpoint registers from an external debugger is not permitted, unless overridden by the <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> authentication interface.</p>
<p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether access to the <a href="ext-oslar_el1.html">OSLAR_EL1</a> register from an external debugger is permitted or not permitted.</p></td></tr></table>
      <p>If EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, then the Effective value of this field is 1.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-19_19-1">TTRF, bit [19]<span class="condition"><br/>When FEAT_TRF is implemented:
                        </span></h4><div class="field">
      <p>Trap Trace Filter controls. Controls whether accesses in modes other than Monitor mode to the trace filter control registers generate a Monitor Trap exception.</p>
    <table class="valuetable"><tr><th>TTRF</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Accesses to <a href="AArch32-htrfcr.html">HTRFCR</a> and <a href="AArch32-trfcr.html">TRFCR</a> are not affected by this control bit.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>When not in Monitor mode, accesses to <a href="AArch32-htrfcr.html">HTRFCR</a> and <a href="AArch32-trfcr.html">TRFCR</a> generate a Monitor Trap exception, unless the access generates a higher priority exception.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-19_19-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-18_18-1">STE, bit [18]<span class="condition"><br/>When FEAT_TRF is implemented:
                        </span></h4><div class="field">
      <p>Secure Trace Enable. This bit enables tracing in Secure state and controls the level of authentication required by an external debugger to enable external tracing.</p>
    <table class="valuetable"><tr><th>STE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Trace is prohibited in Secure state unless overridden by the <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> authentication interface.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Trace in Secure state is not affected by this bit.</p>
        </td></tr></table><p>This bit also controls the level of authentication required by an external debugger to enable external tracing. See <span class="xref">'Register controls to enable self-hosted trace'</span>.</p>
<p>If EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, the PE behaves as if this bit is set to 1.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-18_18-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-17_17-1">SPME, bit [17]<span class="condition"><br/>When FEAT_PMUv3 is implemented and FEAT_Debugv8p2 is implemented:
                        </span></h4><div class="field">
      <p>Secure Performance Monitors Enable. Controls event counting in Secure state.</p>
    <table class="valuetable"><tr><th>SPME</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Event counting is prohibited in Secure state. If <a href="AArch32-pmcr.html">PMCR</a>.DP is 1, <a href="AArch32-pmccntr.html">PMCCNTR</a> is disabled in Secure state. Otherwise, <a href="AArch32-pmccntr.html">PMCCNTR</a> is not affected by this mechanism.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Event counting and <a href="AArch32-pmccntr.html">PMCCNTR</a> are not affected by this mechanism.</p>
        </td></tr></table><p>This field affects the operation of all event counters in Secure state, and if <a href="AArch32-pmcr.html">PMCR</a>.DP is 1, the operation of <a href="AArch32-pmccntr.html">PMCCNTR</a> in Secure state. When <a href="AArch32-pmcr.html">PMCR</a>.DP is 0, <a href="AArch32-pmccntr.html">PMCCNTR</a> is not affected by this field.</p>
<p>If EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, then the Effective value of this field is 1.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-17_17-2"><span class="condition"><br/>When FEAT_PMUv3 is implemented:
                        </span></h4><div class="field">
      <p>Secure Performance Monitors Enable. Controls event counting in Secure state.</p>
    <table class="valuetable"><tr><th>SPME</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>If <span class="function">ExternalSecureNoninvasiveDebugEnabled</span>() is FALSE, event counting is prohibited in Secure state, and if <a href="AArch32-pmcr.html">PMCR</a>.DP is 1, <a href="AArch32-pmccntr.html">PMCCNTR</a> is disabled in Secure state.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Event counting and <a href="AArch32-pmccntr.html">PMCCNTR</a> are not affected by this mechanism.</p>
        </td></tr></table><p>If <span class="function">ExternalSecureNoninvasiveDebugEnabled</span>() is TRUE, the event counters and <a href="AArch32-pmccntr.html">PMCCNTR</a> are not affected by this field.</p>
<p>Otherwise, this field affects the operation of all event counters in Secure state, and if <a href="AArch32-pmcr.html">PMCR</a>.DP is 1, the operation of <a href="AArch32-pmccntr.html">PMCCNTR</a> in Secure state. When <a href="AArch32-pmcr.html">PMCR</a>.DP is 0, <a href="AArch32-pmccntr.html">PMCCNTR</a> is not affected by this field.</p>
<p>If EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, then the Effective value of this field is 1.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-17_17-3"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-16_16">Bit [16]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_14">SPD, bits [15:14]</h4><div class="field">
      <p>AArch32 Secure self-hosted Privileged Debug. Enables or disables debug exceptions from EL3, other than Breakpoint Instruction exceptions.</p>
    <table class="valuetable"><tr><th>SPD</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Legacy mode. Debug exceptions from EL3 are enabled by the authentication interface.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Secure privileged debug disabled. Debug exceptions from EL3 are disabled.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Secure privileged debug enabled. Debug exceptions from EL3 are enabled.</p>
        </td></tr></table><p>Other values are reserved, and have the <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> behavior that they must have the same behavior as <span class="binarynumber">0b00</span>. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.</p>
<p>This field has no effect on Breakpoint Instruction exceptions. These are always enabled.</p>
<p>This field is ignored in Non-secure state.</p>
<p>If debug exceptions from EL3 are enabled, then debug exceptions from Secure EL0 are also enabled.</p>
<p>Otherwise, debug exceptions from Secure EL0 are enabled only if the value of <a href="AArch32-sder.html">SDER</a>.SUIDEN is 1.</p>
<p>If EL3 is not implemented and the Effective value of <a href="AArch32-scr.html">SCR</a>.NS is 0, then the Effective value of this field is <span class="binarynumber">0b11</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, in a system where the PE resets into EL3, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-13_0">Bits [13:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing SDCR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0001</td><td>0b0011</td><td>0b001</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T1 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T1 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif !ELUsingAArch32(EL2) &amp;&amp; SCR_EL3.&lt;NS,EEL2&gt; == '01' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.NS == '0' then
        AArch64.AArch32SystemAccessTrap(EL3, 0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    R[t] = SDCR;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0001</td><td>0b0011</td><td>0b001</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T1 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T1 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif !ELUsingAArch32(EL2) &amp;&amp; SCR_EL3.&lt;NS,EEL2&gt; == '01' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif !ELUsingAArch32(EL3) &amp;&amp; SCR_EL3.NS == '0' then
        AArch64.AArch32SystemAccessTrap(EL3, 0x03);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    if CP15SDISABLE2 == Signal_High then
        UNDEFINED;
    else
        SDCR = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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